Component Library:Sensor Driver for NMH1000  v1.0
Platform agnostic sensor driver interfaces for NMH1000 sensor
nmh1000_regdef.h
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29 
30 /*! File: nmh1000_regdef.h
31 * @brief The \b nmh1000_regdef.h file contains the register definitions for NMH1000 sensor.
32 */
33 
34 #ifndef NMH1000_H_
35 #define NMH1000_H_
36 
37 /**
38  **
39  ** @brief The NMH1000 Sensor Internal Map.
40  */
41 enum {
48  NMH1000_ODR = 0x06,
52 };
53 
54 
55 /*--------------------------------
56 ** Register: STATUS
57 ** Enum: NMH1000_STATUS
58 ** --
59 ** Offset : 0x0 - Status reporting register
60 ** ------------------------------*/
61 typedef union {
62  struct {
63  uint8_t out_b : 1; /* Output Buffer indicate a latched state of the VOUT pin after a transition */
64  /* from either Asserted to Clear or Clear to Asserted. */
65 
66  uint8_t rst_stat : 1; /* Reset Status shall indicate the state-machine reset sequence. */
67 
68  uint8_t _reserved_ : 1;
69  uint8_t opmode : 1; /* The read-only OPMODE shall indicate the mode of the internal */
70  /* state-machine. */
71 
72  uint8_t _reserved_1 : 1;
73  uint8_t mdr : 1; /* Magnetic Data Ready shall indicate the value in register $03 is available */
74  /* for read operation. */
75 
76  uint8_t mdo : 1; /* Magnetic Data Overwrite shall indicate the validity of the value in */
77  /* register $03. */
78 
79  uint8_t output : 1; /* Vout control block state. */
80 
81  } b;
82  uint8_t w;
84 
85 
86 /*
87 ** STATUS - Bit field mask definitions
88 */
89 #define NMH1000_STATUS_OUT_B_MASK ((uint8_t) 0x01)
90 #define NMH1000_STATUS_OUT_B_SHIFT ((uint8_t) 0)
91 
92 #define NMH1000_STATUS_RST_STAT_MASK ((uint8_t) 0x02)
93 #define NMH1000_STATUS_RST_STAT_SHIFT ((uint8_t) 1)
94 
95 #define NMH1000_STATUS_OPMODE_MASK ((uint8_t) 0x08)
96 #define NMH1000_STATUS_OPMODE_SHIFT ((uint8_t) 3)
97 
98 #define NMH1000_STATUS_MDR_MASK ((uint8_t) 0x20)
99 #define NMH1000_STATUS_MDR_SHIFT ((uint8_t) 5)
100 
101 #define NMH1000_STATUS_MDO_MASK ((uint8_t) 0x40)
102 #define NMH1000_STATUS_MDO_SHIFT ((uint8_t) 6)
103 
104 #define NMH1000_STATUS_OUTPUT_MASK ((uint8_t) 0x80)
105 #define NMH1000_STATUS_OUTPUT_SHIFT ((uint8_t) 7)
106 
107 
108 /*
109 ** STATUS - Bit field value definitions
110 */
111 #define NMH1000_STATUS_OUT_B_CLEARED ((uint8_t) 0x00) /* OUT Cleared on previous cycle. */
112 #define NMH1000_STATUS_OUT_B_ASSERTED ((uint8_t) 0x01) /* OUT asserted on previous cycle. */
113 #define NMH1000_STATUS_RST_STAT_RST_SEQ_COMPLETED ((uint8_t) 0x00) /* Reset sequence complete and read operation */
114  /* performed on register $00. */
115 #define NMH1000_STATUS_RST_STAT_RST_SEQ_NOT_COMPLETED ((uint8_t) 0x02) /* Reset sequence not complete. Result of Reset. */
116 #define NMH1000_STATUS_OPMODE_STATE_MACHINE_FAULT ((uint8_t) 0x00) /* ndicates VPP < VSTAND and the device in */
117  /* Standalone mode indicating a state machine fault, */
118  /* since the registers are only accessible in the */
119  /* I2C mode. */
120 #define NMH1000_STATUS_OPMODE_USER_MODE ((uint8_t) 0x08) /* Indicates VPP >= VSTAND and the device in I2C User */
121  /* Mode. */
122 #define NMH1000_STATUS_MDR_DATA_AVAILABLE ((uint8_t) 0x00) /* $03 data available. */
123 #define NMH1000_STATUS_MDR_DATA_NOT_AVAILABLE ((uint8_t) 0x20) /* $03 data not available. Result of Reset. */
124 #define NMH1000_STATUS_MDO_VALIDITY_IN_RANGE ((uint8_t) 0x00) /* Register $03 value is within the range $00 to $1F. */
125 #define NMH1000_STATUS_MDO_VALIDITY_OUT_OF_RANGE ((uint8_t) 0x40) /* Register $03 value is >$1F indicating out-of-range */
126  /* or fault. Result of Reset. */
127 #define NMH1000_STATUS_OUTPUT_VOUT_DRIVEN_TO_VOL ((uint8_t) 0x00) /* The state of VOUT is driven to VOL; Result of */
128  /* Reset. */
129 #define NMH1000_STATUS_OUTPUT_VOUT_DRIVEN_TO_VOH ((uint8_t) 0x80) /* The state of VOUT is driven to VOH. */
130 /*------------------------------*/
131 
132 
133 
134 
135 /*--------------------------------
136 ** Register: CONTROL_REG1
137 ** Enum: NMH1000_CONTROL_REG1
138 ** --
139 ** Offset : 0x01 - Control Register
140 ** ------------------------------*/
141 typedef union {
142  struct {
143  uint8_t rst : 1; /* Internal device Soft Reset. */
144 
145  uint8_t _reserved_ : 1;
146  uint8_t one_short : 1; /* It provides control of the state machine to trigger a single sequence of */
147  /* Compare to Vout Control, then halt. The bit shall clear upon the sequence */
148  /* being completed. */
149 
150  uint8_t auto_mode : 1; /* It provides control of the state machine to enter a sequential autonomous */
151  /* mode cycling from Sleep to Compare to Vout Control, then back to Sleep, */
152  /* etc. The sequence shall be halted when the AUTO is written to 0. */
153 
154  uint8_t i2c_dis : 1; /* Control of the operating mode "on-the'fly" after the device has exited POR */
155  /* or Soft Reset. This allows the user to force the device into standalone */
156  /* mode. */
157 
158  uint8_t v_pol : 1; /* Control of the user-defined OUT pin and resultant OUT_B register bit */
159  /* assert / clear polarity. */
160 
161  } b;
162  uint8_t w;
164 
165 
166 /*
167 ** CONTROL_REG1 - Bit field mask definitions
168 */
169 #define NMH1000_CONTROL_REG1_RST_MASK ((uint8_t) 0x01)
170 #define NMH1000_CONTROL_REG1_RST_SHIFT ((uint8_t) 0)
171 
172 #define NMH1000_CONTROL_REG1_ONE_SHORT_MASK ((uint8_t) 0x04)
173 #define NMH1000_CONTROL_REG1_ONE_SHORT_SHIFT ((uint8_t) 2)
174 
175 #define NMH1000_CONTROL_REG1_AUTO_MODE_MASK ((uint8_t) 0x08)
176 #define NMH1000_CONTROL_REG1_AUTO_MODE_SHIFT ((uint8_t) 3)
177 
178 #define NMH1000_CONTROL_REG1_I2C_DIS_MASK ((uint8_t) 0x10)
179 #define NMH1000_CONTROL_REG1_I2C_DIS_SHIFT ((uint8_t) 4)
180 
181 #define NMH1000_CONTROL_REG1_V_POL_MASK ((uint8_t) 0x20)
182 #define NMH1000_CONTROL_REG1_V_POL_SHIFT ((uint8_t) 5)
183 
184 
185 /*
186 ** CONTROL_REG1 - Bit field value definitions
187 */
188 #define NMH1000_CONTROL_REG1_RST_NO_RESET ((uint8_t) 0x00) /* No reset is forced. */
189 #define NMH1000_CONTROL_REG1_RST_RESET ((uint8_t) 0x01) /* Internal device reset is be forced. */
190 #define NMH1000_CONTROL_REG1_ONE_SHORT_EN ((uint8_t) 0x04) /* Trigger a One-Shot sequence. */
191 #define NMH1000_CONTROL_REG1_AUTO_MODE_HALT ((uint8_t) 0x00) /* Halts or prevents Autonomous mode. */
192 #define NMH1000_CONTROL_REG1_AUTO_MODE_START ((uint8_t) 0x08) /* Start the Autonomous mode. */
193 #define NMH1000_CONTROL_REG1_I2C_DIS_STANDALONE_MODE ((uint8_t) 0x10) /* force the device into i2c standalone mode. */
194 #define NMH1000_CONTROL_REG1_V_POL_ASSERT_VOH_CLR_VOL ((uint8_t) 0x00) /* Assert = VOH, Clear = VOL; Result of Reset */
195 #define NMH1000_CONTROL_REG1_V_POL_ASSERT_VOL_CLR_VOH ((uint8_t) 0x20) /* Assert = VOL, Clear = VOH. */
196 /*------------------------------*/
197 
198 
199 
200 
201 /*--------------------------------
202 ** Register: RESERVED_REG_1
203 ** Enum: NMH1000_RESERVED_REG_1
204 ** --
205 ** Offset : 0x02
206 ** ------------------------------*/
207 typedef uint8_t NMH1000_RESERVED_REG_1_t;
208 
209 
210 /*--------------------------------
211 ** Register: OUT_M_REG
212 ** Enum: NMH1000_OUT_M_REG
213 ** --
214 ** Offset : 0x03 - Report of Magnetic Field Strength
215 ** ------------------------------*/
216 typedef uint8_t NMH1000_OUT_M_REG_t;
217 
218 
219 /*--------------------------------
220 ** Register: USER_ASSERT_THRESH
221 ** Enum: NMH1000_USER_ASSERT_THRESH
222 ** --
223 ** Offset : 0x04 - User selectable output Assert Threshold value from $01 to $1F;provides the capability for the user to override the fixed threshold controlling the output assert condition.
224 ** ------------------------------*/
226 
227 
228 /*--------------------------------
229 ** Register: USER_CLEAR_THRESH
230 ** Enum: NMH1000_USER_CLEAR_THRESH
231 ** --
232 ** Offset : 0x05 - User selectable output Clear Threshold value from $01 to $1F;provides the capability for the user to override the fixed threshold controlling the output clear condition.
233 ** ------------------------------*/
235 
236 
237 /*--------------------------------
238 ** Register: USER_ODR
239 ** Enum: NMH1000_USER_ODR
240 ** --
241 ** Offset : 0x06 - User Setting of Sample Rate(ODR)
242 ** ------------------------------*/
243 typedef union {
244  struct {
245  uint8_t odr : 3;
246  } b;
247  uint8_t w;
249 
250 
251 /*
252 ** USER_ODR - Bit field mask definitions
253 */
254 #define NMH1000_USER_ODR_ODR_MASK ((uint8_t) 0x07)
255 #define NMH1000_USER_ODR_ODR_SHIFT ((uint8_t) 0)
256 
257 
258 /*
259 ** USER_ODR - Bit field value definitions
260 */
261 #define NMH1000_USER_ODR_ODR_LSP ((uint8_t) 0x00) /* Low sample rate selected */
262 #define NMH1000_USER_ODR_ODR_5X_LSP ((uint8_t) 0x01) /* 5*Low sample rate selected */
263 #define NMH1000_USER_ODR_ODR_MSP ((uint8_t) 0x02) /* Medium sample rate selected */
264 #define NMH1000_USER_ODR_ODR_HSP ((uint8_t) 0x04) /* High sample rate selected */
265 #define NMH1000_USER_ODR_ODR_5X_HSP ((uint8_t) 0x05) /* 5*High sample rate selected */
266 #define NMH1000_USER_ODR_ODR_10X_HSP ((uint8_t) 0x06) /* 10*High sample rate selected */
267 #define NMH1000_USER_ODR_ODR_CONFIG_ERR ((uint8_t) 0x07) /* Coniguration error */
268 /*------------------------------*/
269 
270 
271 
272 /*--------------------------------
273 ** Register: RESERVED_REG_2
274 ** Enum: NMH1000_RESERVED_REG_2
275 ** --
276 ** Offset : 0x07
277 ** ------------------------------*/
278 typedef uint8_t NMH1000_RESERVED_REG_2_t;
279 
280 
281 /*--------------------------------
282 ** Register: WHO_AM_I
283 ** Enum: NMH1000_WHO_AM_I
284 ** --
285 ** Offset : 0x08 - Device identification register
286 ** ------------------------------*/
287 typedef uint8_t NMH1000_WHO_AM_I_t;
288 
289 
290 /*--------------------------------
291 ** Register: I2C_ADDR
292 ** Enum: NMH1000_I2C_ADDR
293 ** --
294 ** Offset : 0x09 - I2C Address register
295 ** ------------------------------*/
296 #endif /* NMH1000_H_ */
297 // RESERVED1 : 0x02
298 // RESERVED2 : 0x07
299 // ODR : 0x06
uint8_t NMH1000_RESERVED_REG_1_t
uint8_t NMH1000_RESERVED_REG_2_t
uint8_t NMH1000_USER_CLEAR_THRESH_t
uint8_t NMH1000_USER_ASSERT_THRESH_t
uint8_t NMH1000_WHO_AM_I_t
uint8_t NMH1000_OUT_M_REG_t